This invention pertains to single or multi-port SRAM bit cells with improved resistance to a-particle strike-induced soft-error or single event upset (SEU) effects.
It is well known that the logic state of a static random access memory (SRAM) bit cell can change if an energetic particle such as an alpha (xcex1) particle strikes the cell. Such xe2x80x9csoft-errorxe2x80x9d or xe2x80x9csingle event upsetxe2x80x9d (SEU) effects can occur if an a-particle strike generates, for a sufficient duration, a charge having a magnitude exceeding the critical charge in one of the cell""s storage nodes (i.e. the minimum electrical charge needed to change the cell""s logic state). Since trace amounts of a-particle emitting constituents are unavoidably found in semiconductor packaging, silicon wafers, and especially in the naturally occurring radioactive lead (Pb) used in xe2x80x9cflip-chipxe2x80x9d packaging, any modern integrated circuit having a large amount of SRAM is potentially susceptible to a significant soft-error rate (SER).
The prior art has evolved various techniques for minimizing susceptibility to SEU effects. One approach, typified by U.S. Pat. No. 4,130,892 issued Dec. 19, 1978, is to increase the memory cell""s charging time constant and thereby decrease the cell""s susceptibility to SEU effects. For example, an RC circuit can be interconnected between the two cross-coupled inverter stages in the typical six-transistor (6T) SRAM cell. An undesirable side effect of this approach is that the added capacitance increases the cell""s write time; and, may also reduce the cell""s stability by reducing the magnitude of the cell""s read currents and/or by disrupting the cell""s drawn width to drawn length (W/L) ratio, adversely affecting the cell""s read/write voltage margins which must be kept within well known limits for correct operation of the cell.
Another prior art approach is to add a small amount of capacitance and/or resistance to each of the cell""s storage nodes. However, this significantly increases the cell""s integrated circuit surface area, which is undesirable. The required increase in surface area can be reduced through the use of one or more additional high capacitance mask layers in the device fabrication process, but this increases fabrication costs, may reduce production yields, and may compromise with previously established fabrication quality standards which do not take such additional mask layers into account.
Another approach, typified by U.S. Pat. No. 4,914,629 issued Apr. 3, 1990, is to interconnect a pair of transistors between the inverters. The added transistors provide an increased impedance path which delays the time required for voltage changes to occur at the cell""s storage nodes, thereby decreasing the cell""s susceptibility to SEU effects. However, an xcex1-particle may still strike the drain of one of the added transistors, resulting in an unwanted SEU effect. This problem can be avoided to some extent by usage of P-channel transistors. But a significant SEU problem nonetheless remains and is aggravated in integrated circuit devices fabricated by deep sub-micron processes. Moreover, increased impedance and/or introduction of delay adversely impact cell performance and increase the cell""s integrated circuit surface area.
A further approach, typified by U.S. Pat. No. 5,886,375 issued Mar. 23, 1999, is to connect each of the cell""s storage nodes to an overlying electrode having a textured surface which is separated from a constant potential plate electrode by a dielectric layer. The textured surface of the overlying electrode provides increased capacitance between the overlying electrode and the constant potential plate electrode, thereby increasing the capacitance of the storage node. However, this approach is again subject to the undesirable side effect of the added capacitance increasing the cell""s write time. Furthermore, the extra capacitor layers require non-standard fabrication processes which can increase costs, potentially reduce yields, and increase the complexity of the techniques required to incorporate the resultant SRAM devices in digital circuits.
Yet another approach, typified by U.S. Pat. No. 6,087,849 issued Jul. 11, 2000 is useful in memory cells dominated either by N+ diffusion associated with N-channel field effect transistors (NFETs); or, dominated by P+ diffusion associated with P-channel field effect transistors (PFETs). In the former case, the cell""s switching point is shifted toward the cell""s negative power supply potential; in the latter case, the cell""s switching point is shifted toward the cell""s positive power supply potential. Such shifts make it more difficult for an xcex1-particle strike to cause a faulty transition from a logic xe2x80x9chighxe2x80x9d state to a logic xe2x80x9clowxe2x80x9d state in the former case; and, more difficult for a faulty transition from a logic xe2x80x9clowxe2x80x9d state to a logic xe2x80x9chighxe2x80x9d state to occur in the latter case. However, the low power supply levels prevalent in modern integrated circuit technologies significantly reduce the margins within which such shifts can be made without destabilizing the SRAM bit cell.
A still further approach is to fabricate a keep-out region around each memory cell. The objective of this approach is to ensure that any xcex1-particles emanating from the device""s lead balls are completely absorbed as they pass through the device""s conductive metal and non-conductive inter-layer dielectric (ILD)/oxide layers before reaching the CMOS substrate. However, such regions unavoidably consume an undesirably large area since the lead balls must often be located in excess of 20-80 xcexcm away from the SRAM memory cells. Moreover, keep-out regions will not shield the memory from xcex1-particles emitted by the very wafer material on which the memory is fabricated.
Since most xcex1-particle induced SRAM SEU effects have been observed to result in single-bit errors, error detection and correction (ECC) circuits have been developed to compensate for such errors. However, ECC circuits significantly and undesirably increase a SRAM""s read/write cycle times. Some applications can not tolerate such increased cycle times, even if pipelining techniques are used. For SRAMs with narrow bus widths, the extra time overhead required to process the additional bits generated by the ECC can be significant. In smaller devices, the additional ECC area consumed on the device can easily exceed the size of the memory cells themselves by a significant amount.
This invention addresses the shortcomings of the prior art.
The invention provides an SEU tolerant SRAM bit cell for either six-transistor (6T), eight-transistor (8T), or multi-port RAM cell configurations fabricated in accordance with 0.18 xcexcm or smaller CMOS processes. SEU tolerance is achieved without significantly increasing the cell""s read and write cycle time and negligible impact on cell stability.
In the FIG. 2A 6T embodiment, the bit cell""s NFET pass transistors and PFET pull-up transistors are increased in size (without increasing the size of the pull-down transistors) to achieve a reasonable write margin, and one of three logic/voltage levels are used to address the cell with the aid of the FIG. 2B tri-level word line decoder for each row in the RAM. A high voltage level is used to write data into the cell, a medium voltage level (which yields an acceptable read margin) is used to read data from the cell, and a low voltage level is used if the cell is not being accessed.
In the FIG. 3 8T embodiment, the desired (predefined) write margin is achieved by increasing the size of the bit cell""s PFET pull-up transistors, again without increasing the size of the pull-down transistors; and, by providing a parallel pair of NFET pass transistors for each one of the cell""s two inverters. The additional NFET pass transistors are sized such that if both pass transistors are on, the cell has the desired write margin; and, if only one pass transistor is on each side of the cell, the read margin is within acceptable limits. Two word lines are provided for each bit cell row: one for writing data into the cell and another for use during both writing and reading operations.
The FIG. 4 10T embodiment increases the capability of the cell""s PFET pull-up transistors to inject current into the cell""s storage nodes (S1, S2) whenever read or write operations are not being performed. This is achieved by associating a parallel pair of PFET pull-up transistors 14, 36 with node S2 and associating another parallel pair of PFET pull-up transistors 18, 32 with node S1. Additional circuitry ensures that the extra PFET pull-up transistors are turned on if data is not being written into their respective associated storage nodes and if that node is in a logic high state; otherwise, the extra PFET pull-up-transistors are turned off. PFET pull-up transistors 14, 18 are sized to ensure reasonable write and read margins, and the extra transistors 30, 32, 34, 36 are sized to provide soft-error protection when the cell is not being accessed.
In the FIG. 5A 6T embodiment, the bit cell""s PFET pull-up transistors are increased in size to achieve a reasonable write margin and those transistors"" gate voltages are controllably varied during write operations. Specifically, if the storage node associated with the PFET pull-up transistor is in the logic low state, a logic high gate voltage is applied to that transistor. If the associated storage node is in the logic high state and if data is not being written into the bit cell, the gate voltage is held near ground potential. If the associated storage node is in the logic high state and if data is being written into the bit cell, the gate voltage is maintained at a voltage which yields the appropriate write margin. The FIG. 5B 8T embodiment illustrates gate voltage control during write operations.